`timescale 1ns/1ps
//in wrapper ,all control signals active high
module ram_2p_d64_w32_wrapper (clk,wren,waddr,wdata,rden,raddr,ram_2p_cfg_register,rdata);
  input  clk;
  input  wren;//write enable,active high 
  input [5:0] waddr;//waddr
  input [31:0] wdata;//wdata
  input  rden;//read enable,active high
  input [5:0] raddr;//raddr
  input [9:0] ram_2p_cfg_register;
  output [31:0] rdata;//rdata


ram_2p_d64_w32 U_ram_2p_d64_w32 ( 
.QA(rdata), 
.CLK(clk), 
.CENA(~rden),//read enable,active low 
.CENB(~wren),//write enable,active low
.AA(raddr), 
.AB(waddr), 
.DB(wdata), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);
 
endmodule
